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[Other resource] ram

Description: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Platform: | Size: 2661 | Author: nick | Hits:

[Other resource] ram

Description: fpga中ram的vhdl的经典程序，适用于ALTERA公司器件
Platform: | Size: 1414 | Author: gcy | Hits:

[VHDL-FPGA-Verilog] SRAM@DMA实验

Description: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，然后NIOS　SHELL下C 语言运行。实验SRAM和DMA调度-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling
Platform: | Size: 33792 | Author: xf | Hits:

[Other] ref-ddr-sdram-vhdl

Description: 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
Platform: | Size: 437248 | Author: kevin | Hits:

[VHDL-FPGA-Verilog] ram

Description: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Platform: | Size: 2048 | Author: nick | Hits:

[VHDL-FPGA-Verilog] Sdram_Control_4Port

Description: ALTERA 的关于对SDRAM控制器操作的verilog相关程序，很不错绝对值得借鉴。-ALTERA on the operation of the SDRAM controller Verilog procedures, it is definitely worth a good draw.
Platform: | Size: 13312 | Author: 邹振兴 | Hits:

[VHDL-FPGA-Verilog] altera_ram

Description: 本程序对如何使用altera系列芯片片上ram进行实例演示，采用Verilog HDL语言编写，并使用modelsim与quartus联合进行功能仿真。本原码是红色逻辑开发板的试验程序，值得一看。-This procedure of how to use the altera series chip-chip ram for example demonstration, using Verilog HDL language, and using ModelSim and Quartus functional simulation carried out jointly. Primitive code is red logic development board of the pilot program, worth a visit.
Platform: | Size: 180224 | Author: panyouyu | Hits:

[MiddleWare] ram

Description: fpga中ram的vhdl的经典程序，适用于ALTERA公司器件-FPGA in VHDL ram the classic procedure, applicable to the company ALTERA devices
Platform: | Size: 1024 | Author: gcy | Hits:

[VHDL-FPGA-Verilog] ram_256

Description: 在Quartus中实现256的RAM，经过实际的应用验证，没有问题的-Quartus achieved in 256 of the RAM, through the practical application of verification, no problem
Platform: | Size: 145408 | Author: 郭翠双 | Hits:

[Software Engineering] 20060510191318991

Description: ALTERA公司DDR ram controller资料-ALTERA company DDR ram controller information
Platform: | Size: 2253824 | Author: 盛雪飞 | Hits:

[VHDL-FPGA-Verilog] vga_hex_disp

Description: 该项目可在VGA显示器上显示ＲＡＭ或ＲＯＭ中的十六进制数据，使用ＶｅｒｉｌｏｇＨＤＬ语言编写，在ＱｕａｒｔｕｓＩＩ开发环境下验证。-The Project displays the content of memory cells in the form of hexadecimal numbers. It uses RAM and ROM memory modules available through special functions. This is why before compiling the whole code the user should open mem.v file and change lpm_ram declarations in RAM module and lpm_rom declarations in ROM module into such that are suitable for a particular producer and scheme. There also may appear the necessity of converting .mif files used to memory initialization. The Memory Initialization File is serviced by the Quartus II environment developed by Altera.
Platform: | Size: 18432 | Author: submars | Hits:

[VHDL-FPGA-Verilog] 19854799dul_ram(yk)

Description: 双口RAM的FPGA源码Altera 活XIinx或ATmel公司都可以-Dual-port RAM of the FPGA source
Platform: | Size: 3072 | Author: gadan | Hits:

[Other] my_ram_vhdl

Description: how to infer ram for fpga altera xilinx
Platform: | Size: 1024 | Author: yusuf.abdullah | Hits:

[VHDL-FPGA-Verilog] miffile

Description: 用matlab产生mif文件。(Altera的EDA软件，如maxplus，quartus等用到的初始化rom，ram等的文件格式)-Mif files generated by matlab. (Altera' s EDA software, such as maxplus, quartus used to initialize and so on rom, ram, such as the file format)
Platform: | Size: 1024 | Author: 何亮 | Hits:

[VHDL-FPGA-Verilog] ram

Description: 基于altera ep2c8双口RAM -Altera ep2c8-based dual-port RAM
Platform: | Size: 884736 | Author: 秦学富 | Hits:

[VHDL-FPGA-Verilog] Guagle_wave

Description: altera 的存储器IP核的初始化mif文件生成器，可任意点数和任意波形-Initial altera s ip core of ROM or RAM need .mif file,use this software you can generate it ,any wave
Platform: | Size: 216064 | Author: chenlei | Hits:

[VHDL-FPGA-Verilog] ram

Description: 使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个RAM存储器。-The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a RAM memory.
Platform: | Size: 198656 | Author: Daisy | Hits:

[VHDL-FPGA-Verilog] Example-b4-1

Description: Altera基本宏功能的产生和实现方法.定制一个双端口RAM，DualPortRAM,Quartus II仿真器中做门级仿真,在ModelSim中对这个工程进行RTL级仿真.-Altera basic macro functionality of the generation and realization. Customize a dual-port RAM, DualPortRAM, Quartus II simulator to do gate level simulation, on the ModelSim RTL-level simulation of this works.
Platform: | Size: 303104 | Author: Gorce | Hits:

[VHDL-FPGA-Verilog] ram_fifo

Description: Altera RAM FIFOIP核，实现对FIFO的读写，对满信号和空信号进行判断.-altera ram fifo ip core
Platform: | Size: 3232768 | Author: xuguo | Hits:

[Embeded-SCM Develop] gen_mif---altera-RAM

Description: ram读取，本例程详细的介绍了RAM的编写，读取，地址的设置等-Read ram, this routine is detailed introduced the ram to write, read, address Settings, and so on
Platform: | Size: 2048 | Author: liuliang | Hits:
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